1. Technical Field
The present invention relates generally to semiconductor devices, and more particularly, to a method of forming low capacitance back end of the line (BEOL) wiring, and the structure so formed.
2. Related Art
When forming CMOS, BiCMOS, SiGe, and other similar devices, it is desirable to minimize capacitance. Likewise, there is a continuing desire in the industry to reduce device size. Therefore, there is a need in the industry for a method of forming a semiconductor device that addresses these and other issues.